Semiconductor power device is one of the major pillars supporting modern day electronics industry. As part of the ongoing trend due to ever increasing chip integration density with concomitant higher power handling ability, low power consumption and low cost, copper wire becomes attractive in replacement of gold wire and Aluminum wire for use in wire bonding as copper wire provides the most cost effective solution to achieve a same design goal of connection loss. The major technical difficulty is its hardness, which requires increasing metallization thickness on the power semiconductor chip to accommodate copper wire bonding. Metal thickness in the range of 3 μm-6 μm (1 μm=1×10−6 meter) is usually required. Semiconductor power devices using traditional bonding wires use a single hot metal layer in the range from 1-3 micron to serve as both contact and bonding pad. Hot Al metal is used for its good step coverage to provide reliable contact within the contact holes as cold Al metal tends to cause voids within contact holes resulting in reliability failure. This is becoming more significant as the advance of technology improves the semiconductor area usage efficiency through the shrinkage of feature size. For example, the wall-to-wall pitch size of some of power MOSFETs in use today are in the order of 1 micron, leading to smaller contact holes dimension and tighten mask alignment tolerance. However the attribute of good step coverage of hot metal would degrade the sharpness of alignment mark for later masking process thus requiring larger tolerance margin while increasing the thickness of metal layer, leading to low semiconductor area usage efficiency. It is therefore desirable to develop new and improved approaches for deposition of thick metal layer in the range of 3-6 micron that would provide both reliable contact and effective alignment marks.